A flip chip is generally a monolithic semiconductor device, such as an integrated circuit, having bead-like terminals formed on one surface of the chip. The terminals serve to both secure the chip to a circuit board and electrically connect the flip chip's circuitry to a conductor pattern formed on the circuit board, which may be a ceramic substrate, printed wiring board, flexible circuit, or a silicon substrate. Due to the numerous functions typically performed by the microcircuitry of a flip chip, a relatively large number of terminals are required. The size of a typical flip chip is generally on the order of a few millimeters per side, resulting in the terminals being crowded along the perimeter of the flip chip. As a result, flip chip conductor patterns are typically composed of numerous individual conductors, often spaced on the order of about 0.008 inch apart.
Because of the fine patterns of the terminals and conductor pattern, soldering a flip chip to its conductor pattern requires a significant degree of precision. Reflow solder techniques are widely utilized in the soldering of flip chips. Such techniques typically involve forming solder bumps on the surface of the flip chip using methods such as electrodeposition, by which a quantity of solder is accurately deposited on one surface of the flip chip. Heating the solder above its melting temperature serves to form the characteristic solder bumps. The chip is then soldered to the conductor pattern by registering the solder bumps with their respective conductors, and reheating, or reflowing, the solder so as to metallurgically and electrically bond the chip to the conductor pattern.
Deposition and reflow of the solder must be precisely controlled not only to coincide with the spacing of the terminals and the size of the conductors, but also to control the height of the solder bumps after soldering. As is well known in the art, controlling the height of solder bumps after reflow is necessary in order to prevent the surface tension of the molten solder bumps from drawing the flip chip excessively close to the substrate during the reflow operation. Sufficient spacing between the chip and its substrate is necessary for enabling stress relief during thermal cycles, allowing penetration of cleaning solutions for removing undesirable residues, and enabling the penetration of mechanical bonding and encapsulation materials between the chip and the substrate.
Solder bump height is typically controlled by limiting the size of the exposed conductor area to which the solder bump is allowed to reflow. This approach, represented in FIG. 1, conventionally involves the use of a solder stop 18, such as a solder mask or a printed dielectric mask, which covers or alters the conductor 14 in the bump reflow region in order to limit the area over which the solder bump 16 can reflow. Physics dictates that, within a certain range, a smaller reflow area results in a greater solder bump height after reflow for a given quantity of solder, though an excessively small reflow area tends to cause the solder bump to collapse, thereby significantly reducing the solder bump height. By properly limiting the degree to which the molten solder can laterally expand during reflow, the height of the solder bumps 16, and therefore the spacing between a chip 12 and a substrate 10, can be closely controlled by depositing an appropriate amount of solder at each terminal location. A variation of the above approach is illustrated in U.S. Pat. No. 4,764,804 to Sahara et al., in which an I/O solder bump is contained between and within a pair of recesses formed in the flip chip surface and the opposing surface of a substrate. A unique though related technique is disclosed in U.S. patent application Ser. No. (Attorney's Docket No. G-6211), assigned to the assignee of this invention, in which laser-formed solder stops are used to limit the flow of molten solder during reflow.
While the techniques for using masks are accepted and used in the art, certain shortcomings exist which are related to processing costs and accuracy. For example, printed and photoimaged dielectric masks do not provide adequate positional accuracy for certain flip chips, particularly flip chips with fine pitch solder bumps. The cost of obtaining the required accuracy may be prohibitive. In addition, although laser-formed solder stops, as taught by U.S. patent application Ser. No. (Attorney's Docket No. G-6211), may provide the necessary accuracy, it may be desirable to minimize processing time and costs.
Accordingly, it would be desirable if a process were available by which the height of a flip chip's solder bumps could be closely controlled without the conventional need for using printed or photoimaged solder masks, or laser-formed solder stops. A preferred process would be capable of a high degree of positional accuracy without adding processing steps, time or capital to the conventional processing of printed circuit board and ceramic substrates, as well as flex, silicon and various other substrates.